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| rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adsp-216x one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 dsp microcomputers with rom functional block diagram serial ports sport 1 sport 0 memory timer shifter mac alu arithmetic units dag 2 dag 1 data address generators external data bus external address bus program memory data memory data memory data data memory address program memory address program memory data program sequencer adsp-2100 core summary 16-bit fixed-point dsp microprocessors with on-chip memory enhanced harvard architecture for three-bus performance: instruction bus and dual data buses independent computation units: alu, multiplier/ accumulator and shifter single-cycle instruction execution and multifunction instructions on-chip program memory rom and data memory ram integrated i/o peripherals: serial ports, timer features 25 mips, 40 ns maximum instruction rate (5 v) separate on-chip buses for program and data memory program memory stores both instructions and data (three-bus performance) dual data address generators with modulo and bit-reverse addressing efficient program sequencing with zero-overhead looping: single-cycle loop setup double-buffered serial ports with companding hardware, automatic data buffering and multichannel operation three edge- or level-sensitive interrupts low power idle instruction plcc and mqfp packages general description the adsp-216x family processors are single-chip micro- computers optimized for digital signal processing (dsp) and other high speed numeric processing applications. the adsp-216x processors are all built upon a common core with adsp-2100. each processor combines the core dsp architec- turecomputation units, data address generators and program sequencerwith features such as on-chip program rom and data memory ram, a programmable timer and two serial ports. the adsp-2165/adsp-2166 also adds program memory and power-down mode. this data sheet describes the following adsp-216x family processors: adsp-2161/adsp-2162/ adsp-2163/adsp-2164 custom rom-programmed dsps : adsp-2165/adsp-2166 rom-programmed adsp-216x processors with power-down and larger on-chip memories (12k pro- gram memory rom, 1k program memory ram, 4k data memory ram) fabricated in a high speed, submicron, double-layer metal cmos process, the highest-performance adsp-216x proces- sors operate at 25 mhz with a 40 ns instruction cycle time. every instruction can execute in a single cycle. fabrication in cmos results in low power dissipation. the adsp-2100 familys flexible architecture and compre- hensive instruction set support a high degree of parallelism. in one cycle the adsp-216x can perform all of the following operations: ? generate the next program address ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computation ? receive and transmit data via one or two serial ports table i shows the features of each adsp-216x processor. the adsp-216x series are memory-variant versions of the adsp-2101 and adsp-2103 that contain factory-programmed on-chip rom program memory. these devices offer different amounts of on-chip memory for program and data storage. table i shows the features available in the adsp-216x series of custom rom-coded processors. the adsp-216x products eliminate the need for an external boot eprom in your system, and can also eliminate the need for any external program memory by fitting the entire applica- tion program in on-chip rom. these devices thus provide an excellent option for volume applications where board space and system cost constraints are of critical concern.
rev. 0 adsp-216x C2C table of contents summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 1 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 architecture overview . . . . . . . . . . . . . . . . . . . . 3 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin function descriptions . . . . . . . . . . . . . . . . . . 6 program memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7 program memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 data memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power-down control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 entering power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 exiting power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 low power idle instruction . . . . . . . . . . . . . . . . . . . . . . . 10 adsp-216x prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ordering procedure for adsp-216x rom processors . . . . 10 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 specificationsCrecommended operating conditions (adsp-2161/adsp-2163/adsp-2165) . . . . . . . . . . . . . . 13 electrical characteristics . . . . . . . . . . . . . . . . 13 absolute maximum ratings . . . . . . . . . . . . . . . . 13 specificationsCsupply current and power (adsp-2161/adsp-2163/adsp-2165) . . . . . . . . . . . . . . 14 power dissipation example . . . . . . . . . . . . . . . . . 15 environmental conditions . . . . . . . . . . . . . . . . 15 capacitive loading . . . . . . . . . . . . . . . . . . . . . . . . . 15 specificationsC (adsp-2161/adsp-2163/adsp-2165) . . . . . . . . . . . . . . 16 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output enable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 specificationsCrecommended operating conditions (adsp-2162/adsp-2164/adsp-2166) . . . . . . . . . . . . . . 17 electrical characteristics . . . . . . . . . . . . . . . . 17 absolute maximum ratings . . . . . . . . . . . . . . . . 17 specificationsCsupply current and power (adsp-2162/adsp-2164/adsp-2166) . . . . . . . . . . . . . . 18 power dissipation example . . . . . . . . . . . . . . . . . 19 environmental conditions . . . . . . . . . . . . . . . . 19 capacitive loading . . . . . . . . . . . . . . . . . . . . . . . . . 19 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output enable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 timing parameters (adsp-2161/adsp-2163/adsp-2165) . . . . . . . . . . . . . . 21 general notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 timing notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 memory requirements . . . . . . . . . . . . . . . . . . . . . . 21 clock signals and reset . . . . . . . . . . . . . . . . . . . 22 interrupts and flags . . . . . . . . . . . . . . . . . . . . . . 23 bus request/bus grant . . . . . . . . . . . . . . . . . . . . . 24 memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 memory write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 timing parameters (adsp-2162/adsp-2164/adsp-2166) . . . . . . . . . . . . . . 28 general notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 timing notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 memory requirements . . . . . . . . . . . . . . . . . . . . . . 28 clock signals and reset . . . . . . . . . . . . . . . . . . . 29 interrupts and flags . . . . . . . . . . . . . . . . . . . . . . . 30 bus request/bus grant . . . . . . . . . . . . . . . . . . . . . 31 memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 memory write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 pin configurations 68-lead plcc (adsp-216x) . . . . . . . . . . . . . . . . . . . . . 35 80-lead mqfp (adsp-216x) . . . . . . . . . . . . . . . . . . . . . 36 package outline dimensions 68-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 80-lead mqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 rev. 0 adsp-216x C3C table i. adsp-216x rom-programmed processor features feature 2161 2162 2163 2164 2165 2166 data memory (ram) 1/2k 1/2k 1/2k 1/2k 4k 4k program memory (rom) 8k 8k 4k 4k 12k 12k program memory (ram) 1k 1k timer ?????? serial port 0 (multichannel) ?????? serial port 1 ?????? supply voltage 5 v 3.3 v 5 v 3.3 v 5 v 3.3 v speed grades (instruction cycle time) 10.24 mhz (97.6 ns) ?? 13.00 mhz ( 76.9 ns ) ? 16.67 mhz (60 ns) ?? ? 20.00 mhz ( 50 ns ) ? 25 mhz (40 ns) ?? packages 68-lead plcc ???? 80-lead mqfp ?????? temperature grades k commercial, 0 c to +70 c ?????? b industrial, C40 c to +85 c ?????? development tools the adsp-216x processors are supported by a complete set of tools for system development. the adsp-2100 family devel- opment software includes c and assembly language tools that allow programmers to write code for any of the adsp-216x processors. the ansi c compiler generates adsp-216x assem- bly source code, while the runtime c library provides ansi- standard and custom dsp library routines. the adsp-216x assembler produces object code modules that the linker com- bines into an executable file. the processor simulators provide an interactive instruction-level simulation with a reconfigurable, windowed user interface. a prom splitter utility generates prom programmer compatible files. ez-ice ? in-circuit emulators allow debugging of adsp-21xx systems by providing a full range of emulation functions such as modification of memory and register values and execution breakpoints. ez-lab ? demonstration boards are complete dsp systems that execute eprom-based programs. the ez-kit lite is a very low-cost evaluation/development platform that contains both the hardware and software needed to evaluate the adsp-21xx architecture. additional details and ordering information are available in the adsp-2100 family software & hardware development tools data sheet (adds-21xx-tools). this data sheet can be requested from any analog devices sales office or distributor. additional information this data sheet provides a general overview of adsp-216x processor functionality. for detailed design information on the architecture and instruction set, refer to the adsp-2100 family users manual , third edition, available from analog devices. architecture overview figure 1 shows a block diagram of the adsp-216x architecture. the processors contain three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add, and multiply/subtract opera- tions. the shifter performs logical and arithmetic shifts, normal- ization, denormalization, and derive exponent operations. the shifter can be used to efficiently implement numeric format control including multiword floating-point representations. the internal result (r) bus directly connects the computational units so that the output of any unit may be used as the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient use of these computational units. the sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. with internal loop counters and loop stacks, the adsp-216x executes looped code with zero overheadno explicit jump instructions are required to main- tain the loop. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. the circular buffering feature is also used by the serial ports for automatic data transfers to (and from) on- chip memory. ez-ice and ez-lab are registered trademarks of analog devices, inc. rev. 0 adsp-216x C4C efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma, dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd, dmd) share a single external data bus. the bms , dms and pms signals indicate which memory space is using the external buses. program memory can store both instructions and data, permit- ting the adsp-216x to fetch two operands in a single cycle, one from program memory and one from data memory. the processor can fetch an operand from on-chip program memory and the next instruction in the same cycle. the memory interface supports slow memories and memory- mapped peripherals with programmable wait state generation. external devices can gain control of the processors buses with the use of the bus request/grant signals ( br , bg ). one bus grant execution mode (go mode) allows the adsp- 216x to continue running from internal memory. a second execution mode requires the processor to halt while buses are granted. each adsp-216x processor can respond to several different interrupts. there can be up to three external interrupts, configured as edge- or level-sensitive. internal interrupts can be generated by the timer and serial ports. there is also a master reset signal. booting circuitry provides for loading on-chip program memory automatically from byte-wide external memory. after reset, three wait states are automatically generated. this allows, for example, a 60 ns adsp-2161 to use a 200 ns eprom as external boot memory. multiple programs can be selected and loaded from the eprom with no additional hardware. the data receive and transmit pins on sport1 (serial port 1) can be alternatively configured as a general-purpose input flag and output flag. you can use these pins for event signalling to and from an external device. a programmable interval timer can generate periodic interrupts. a 16-bit count register (tcount) is decremented every n cycles, where nC1 is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the adsp-216x processors include two synchronous serial ports (sports) for serial communications and multiprocessor communication. all of the adsp-216x processors have two serial ports (sport0, sport1). the serial ports provide a complete synchronous serial interface with optional companding in hardware. a wide variety of framed or frameless data transmit and receive modes of opera- tion are available. each sport can generate an internal pro- grammable serial clock or accept an external serial clock. each serial port has a 5-pin interface consisting of the following signals: signal name function sclk serial clock (i/o) rfs receive frame synchronization (i/o) tfs transmit frame synchronization (i/o) dr serial data receive dt serial data transmit output regs input regs output regs input regs output regs input regs data address generator #1 data address generator #2 instruction register program sequencer program memory sram & rom boot address generator timer pma bus dma bus pmd bus dmd bus 24 16 bus exchange companding circuitry transmit reg receive reg serial port 1 transmit reg receive reg serial port 0 5 5 16 r bus alu mac shifter pma bus 14 14 pma bus data memory sram external data bus external address bus mux mux 24 14 24 pma bus 16 pma bus 16 figure 1. adsp-216x block diagram rev. 0 adsp-216x C5C the adsp-216x serial ports offer the following capabilities: bidirectional each sport has a separate, double-buffered transmit and receive function. flexible clocking each sport can use an external serial clock or generate its own clock internally. flexible framing the sports have independent framing for the transmit and receive functions; each function can run in a frameless mode or with frame synchronization signals inter- nally generated or externally generated; frame sync signals may be active high or inverted, with either of two pulsewidths and timings. different word lengths each sport supports serial data word lengths from 3 to 16 bits. companding in hardware each sport provides optional a-law and m -law companding according to ccitt recommen- dation g.711. flexible interrupt scheme receive and transmit functions can generate a unique interrupt upon completion of a data word transfer. autobuffering with single-cycle overhead each sport can automatically receive or transmit the contents of an entire circular data buffer with only one overhead cycle per data word; an interrupt is generated after the transfer of the entire buffer is completed. multichannel capability ( sport0 only ) sport0 pro- vides a multichannel interface to selectively receive or transmit a 24-word or 32-word, time-division multiplexed serial bit stream; this feature is especially useful for t1 or cept interfaces, or as a network communication scheme for multiple processors. alternate configuration sport1 can be alternatively configured as two external interrupt inputs ( irq0 , irq1 ) and the flag in and flag out signals (fi, fo). interrupts the adsp-216xs interrupt controller lets the processor re- spond to interrupts with a minimum of overhead. up to three external interrupt input pins, irq0 , irq1 and irq2 , are pro- vided. irq2 is always available as a dedicated pin; irq1 and irq0 may be alternately configured as part of serial port 1. the adsp-216x also supports internal interrupts from the timer and the serial ports. the interrupts are internally prioritized and individually maskable (except for reset which is nonmaskable). the irqx input pins can be programmed for either level- or edge-sensitivity. the interrupt priorities for each adsp-216x processor are shown in table ii. table ii. interrupt vector addresses and priority interrupt adsp-216x interrupt source vector address reset startup 0x0000 irq2 or power-down 0x0004 (high priority) sport0 transmit 0x0008 sport0 receive 0x000c sport1 transmit or irq1 0x0010 sport1 receive or irq0 0x0014 timer 0x0018 (low priority) the adsp-216x uses a vectored interrupt scheme: when an interrupt is acknowledged, the processor shifts program control to the interrupt vector address corresponding to the interrupt received. interrupts can be optionally nested so that a higher priority interrupt can preempt the currently executing interrupt service routine. each interrupt vector location is four instruc- tions in length so that simple service routines can be coded entirely in this space. longer service routines require an addi- tional jump or call instruction. individual interrupt requests are logically anded with the bits in the imask register; the highest-priority unmasked interrupt is then selected. the interrupt control register, icntl , allows the external interrupts to be set as either edge- or level-sensitive. depending on bit 4 in icntl , interrupt service routines can either be nested (with higher priority interrupts taking precedence) or be processed sequentially (with only one interrupt service active at a time). the interrupt force and clear register, ifc, is a write-only regis- ter that contains a force bit and a clear bit for each interrupt. when responding to an interrupt, the astat, mstat and imask status registers are pushed onto the status stack and the pc counter is loaded with the appropriate vector address. the status stack is seven levels deep to allow interrupt nesting. the stack is automatically popped when a return from the inter- rupt instruction is executed. pin definitions pin function descriptions show pin definitions for the adsp- 216x processors. any inputs not used must be tied to v dd . system interface figure 3 shows a typical system for the adsp-216x with two serial i/o devices, an optional external program and data memory. a total of 12k words of data memory and 15k words of program memory is addressable. programmable wait-state generation allows the processors to easily interface to slow external memories. the adsp-216x processors also provide either: one external interrupt ( irq2 ) and two serial ports (sport0, sport1), or three external interrupts ( irq2 , irq1 , irq0 ) and one serial port (sport0). clock signals the adsp-216x processors clkin input may be driven by a crystal or by a ttl-compatible external clock signal. the clkin input may not be halted or changed in frequency during operation, nor operated below the specified low frequency limit. if an external clock is used, it should be a ttl-compatible signal running at the instruction rate. the signal should be connected to the processors clkin input; in this case, the xtal input must be left unconnected. because the adsp-216x processors include an on-chip oscilla- tor circuit, an external crystal may also be used. the crystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 2. a parallel- resonant, fundamental frequency, microprocessor-grade crystal should be used. rev. 0 adsp-216x C6C clkin clkout xtal adsp-216x figure 2. external crystal connections a clock output signal (clkout) is generated by the processor, synchronized to the processors internal cycles. reset the reset signal initiates a complete reset of the adsp-216x. the reset signal must be asserted when the chip is powered up to assure proper initialization. if the reset signal is applied during initial power-up, it must be held long enough to allow the processors internal clock to stabilize. if reset is activated at any time after power-up and the input clock frequency does not change, the processors internal clock continues and does not require this stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is applied to the processor and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 t ck cycles will ensure that the pll has locked (this does not, however, include the crystal oscillator start-up time). during this power-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulsewidth specification, t rsp . to generate the reset signal, use either an rc circuit with an external schmidt trigger or a commercially available reset ic. (do not use only an rc circuit.) the reset input resets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the mstat register. when reset is released, the boot loading sequence is performed (provided there is no pending bus request and the chip is configured for booting, with mmap = 0). the first instruction is then fetched from internal program memory location 0x0000. pin function descriptions pin # of input/ name(s) pins output function address 14 o address outputs for program, data and boot memory. data 1 24 i/o data i/o pins for program and data memories. input only for boot memory, with two msbs used for boot memory addresses. unused data lines may be left floating. reset 1 i processor reset input irq2 1 i external interrupt request #2 br 2 1 i external bus request input bg 1 o external bus grant output pms 1 o external program memory select dms 1 o external data memory select bms 1 o boot memory select rd 1 o external memory read enable wr 1 o external memory write enable mmap 1 i memory map select input clkin, xtal 2 i external clock or quartz crystal input clkout 1 o processor clock output v dd power supply pins gnd ground pins sport0 5 i/o serial port 0 pins ( tfs0, rfs0, dt0, dr0, sclk0 ) sport1 5 i/o serial port 1 pins ( tfs1, rfs1, dt1, dr1, sclk1 ) or interrupts and flags: irq0 (rfs1) 1 i external interrupt request #0 irq1 (tfs1) 1 i external interrupt request #1 fi (dr1) 1 i flag input pin fo (dt1) 1 o flag output pin pwdack 3 1 o indicates when the processor has entered power-down. pwdflag 3 1 i low-to-high transition of the power-down flag. input pin can be used to terminate power-down. notes 1 unused data bus lines may be left floating. 2 br must be tied high (to v dd ) if not used. 3 only on adsp-2165/adsp-2166. rev. 0 adsp-216x C7C program memory interface the on-chip program memory address bus (pma) and on-chip program memory data bus (pmd) are multiplexed with the on- chip data memory buses (dma, dmd), creating a single exter- nal data bus and a single external address bus. the external data bus is bidirectional and is 24 bits wide to allow instruction fetches from external program memory. program memory may contain code and data. the external address bus is 14 bits wide. for the adsp-216x, these lines can directly address up to 16k words, of which 2k are on-chip. the data lines are bidirectional. the program memory select ( pms ) signal indicates accesses to program memory and can be used as a chip select signal. the write ( wr ) signal indicates a write operation and is used as a write strobe. the read ( rd ) signal indicates a read operation and is used as a read strobe or output enable signal. the adsp-216x processors write data from their 16-bit regis- ters to 24-bit program memory using the px register to provide the lower eight bits. when the processor reads 16-bit data from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the px register. the program memory interface can generate 0 to 7 wait states for external memory devices; default is to 7 wait states after reset . program memory maps program memory can be mapped in two ways, depending on the state of the mmap pin. figure 4 shows the program memory map for the adsp-2165/adsp-2166. figures 5 and 6 show the program memory maps for the adsp-2161/adsp-2162 and adsp-2163/adsp-2164, respectively. adsp-2165/adsp-2166 when mmap = 0, on-chip program memory rom occupies 12k words beginning at address 0x0000. internal program memory ram occupies 1k words beginning at address 0x3000. off-chip program memory uses the 2k words beginning at address 0x3800. the adsp-2165/adsp-2166 does not support boot memory. when mmap = 1, 2k words of off-chip program memory begin at address 0x0000. 10k words of on-chip program memory rom at 0x800 to 0x2fff, and the remainder 2k words of program memory rom is at 0x3800 to 0x3fff. internal pro- gram memory ram occupies 1k words at address 0x300 to 0x33ff. 0x0000 2k external mmap = 0 12k 3 24 internal rom 10k 3 24 internal rom 1k 3 24 ram reserved 2k 3 24 external 2k 3 24 internal rom 1k 3 24 ram reserved mmap = 1 0x2fff 0x3000 0x33ff 0x3400 0x37ff 0x3800 0x3fff 0x0000 0x2fff 0x3000 0x33ff 0x3400 0x37ff 0x3800 0x3fff 0x07ff 0x0800 figure 4. adsp-2165/adsp-2166 program memory maps adsp-2161/adsp-2162 when mmap = 0, on-chip program memory rom occupies 8k words beginning at address 0x0000. off-chip program memory uses the remaining 8k words beginning at address 0x2000. when mmap = 1, 2k words of off-chip program memory begin at address 0x0000. 6k words of on-chip program memory rom are at 0x0800 to 0x1ff0, and the remainder 2k words of pro- gram memory rom is at 0x3800 to 0x3fff. an additional 6k of off-chip program memory is at 0x2000 to 0x37ff. mmap = 0 8k internal rom reserved mmap = 1 0x0000 0x1ff0 0x1fff 0x2000 0x3fff 2k external reserved 0x0000 0x1ff0 0x1fff 0x2000 0x3fff 6k internal rom 6k external 2k internal rom 0x7fff 0x0800 0x37ff 0x3800 8k external figure 5. adsp-2161/adsp-2162 program memory maps adsp-216x reset irq2 br bg mmap serial port 0 serial port 1 pms rd dms bms address data clkin xtal clkout v dd gnd clock or crystal 34 sclk sclk rfs or irq0 tfs or irq1 dt or fo dr or fi rfs tfs dt dr serial device (optional) serial device (optional) program memory (optional) ad cs oe we data memory & peripherals ad cs oe we 14 rw 16 d23-8 24 figure 3. basic system configuration rev. 0 adsp-216x C8C adsp-2163/adsp-2164 when mmap = 0, on-chip program memory rom occupies 4k words beginning at address 0x0000. off-chip program memory uses the remaining 12k words beginning at address 0x1000. when mmap = 1, 2k words of off-chip program memory begin at address 0x0000. 2k words of on-chip program memory rom is at 0x0800 to 0x0ff0, and the remainder 2k words of pro- gram memory rom is at 0x3800 to 0x3fff. an additional 10k of off-chip program memory is at 0x1000 to 0x37ff. mmap = 0 4k internal rom reserved mmap = 1 0x0000 0x0ff0 0x0fff 0x1000 0x3fff 2k external reserved 0x0000 0x0ff0 0x0fff 0x1000 0x3fff 2k internal rom 10k external 2k internal rom 0x07ff 0x0800 0x37ff 0x3800 12k external figure 6. adsp-2163/adsp-2164 program memory maps data memory interface the data memory address bus (dma) is 14 bits wide. the bidirectional external data bus is 24 bits wide, with the upper 16 bits used for data memory data (dmd) transfers. the data memory select (dms) signal indicates access to data memory and can be used as a chip select signal. the write (wr) signal indicates a write operation and can be used as a write strobe. the read (rd) signal indicates a read operation and can be used as a read strobe or output enable signal. the adsp-216x processors support memory-mapped i/o, with the peripherals memory-mapped into the data memory address space and accessed by the processor in the same manner as data memory. data memory map for the adsp-2165/adsp-2166, on-chip data memory ram resides in the 4k words beginning at address 0x2000, as shown in figure 7. data memory locations from 0x3000 to the end of data memory at 0x3fff are reserved. control and status regis- ters for the system, timer, wait-state configuration, and serial port operations are located in this region of memory. the remaining 8k of data memory is located off-chip. this external data memory is divided into three zones, each associ- ated with its own wait-state generator. this allows slower pe- ripherals to be memory-mapped into data memory for which wait states are specified. by mapping peripherals into different zones, you can accommodate peripherals with different w ait- state requirements. all zones default to 7 wait states after reset . 0x0000 4k 3 16 memory-mapped registers & reserved 0x0800 address (hex) 4k 3 16 internal 6k external dwait2 1k external dwait0 1k external dwait1 0x0400 0x2000 0x3000 0x3fff external ram internal ram figure 7. adsp-2165/adsp-2166 data memory map adsp-2161/adsp-2162/adsp-2163/adsp-2164 for the adsp-2161/adsp-2162/adsp-2163/adsp-2164, on- chip data memory ram resides in the 512 words beginning at address 0x3800, also shown in figure 8. data memory locations from 0x3a00 to the end of data memory at 0x3fff are reserved. control and status registers for the system, timer, wait-state configuration, and serial port operations are located in this region of memory. 0x0000 512 adsp-2161/62/63/64 0x0800 address (hex) 10k external dwait2 1k external dwait0 1k external dwait1 0x0400 0x3000 0x3c00 0x3fff external ram internal ram 1k external dwait3 1k external dwait4 memory-mapped control registers & reserved 0x3a00 0x3800 0x3400 figure 8. adsp-2161/adsp-2162/adsp-2163/adsp-2164 data memory map the remaining 14k of data memory is located off-chip. this external data memory is divided into five zones, each associated with its own wait-state generator. this allows slower peripherals to be memory-mapped into data memory for which wait states are specified. by mapping peripherals into different zones, you can accommodate peripherals with different wait-state require- ments. all zones default to seven wait states after reset . rev. 0 adsp-216x C9C bus interface the adsp-216x processors can relinquish control of their data and address buses to an external device. when the external device requires control of the buses, it asserts the bus request signal ( br ). if the adsp-216x is not performing an external memory access, it responds to the active br input in the next cycle by: ? three-stating the data and address buses and the pms, dms , bms , rd , wr output drivers, ? asserting the bus grant (bg) signal, and halting program execution. if the go mode is set, however, the adsp-216x will not halt program execution until it encounters an instruction that requires an external memory access. if the adsp-216x is performing an external memory access when the external device asserts the br signal, it will not three- state the memory interfaces or assert the bg signal until the cycle after the access completes (up to eight cycles later depend- ing on the number of wait states). the instruction does not need to be completed when the bus is granted; the adsp-21xx will grant the bus between two memory accesses if an instruction requires more than one external memory access. when the br signal is released, the processor releases the bg signal, re-enables the output drivers and continues program execution from the point at which it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. if this feature is not used, the br input should be tied high (to v dd ). power-down the adsp-2165/adsp-2166 processors have a low power feature that lets the processor enter a very low power dormant state through hardware or software control. a list of power- down features follows: ? processor registers and on-chip memory contents are main- tained during power-down. ? power-down mode holds the processor in cmos standby with a maximum current of less than 100 m a in some modes. ? support for an externally generated ttl or cmos proces- sor clock. the external clock can continue running during power-down without affecting the lowest power rating. ? support for crystal operation includes disabling the oscillator to save power. (the processor automatically waits 4096 clkin cycles for the crystal oscillator to start and stabilize). ? when power-down mode is enabled, powering down of the processor can be initiated either by externally generated irq2 interrupt or by using the irq2 force bit in the ifc register. ? power-down acknowledge pin (pwdack) indicates when the processor has entered power-down. ? interrupt support allows an unlimited number of instructions to be executed before optionally powering down. ? context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. ? low-to-high transition of the power-down flag input pin (pwdflag) can be used to terminate power-down. ? the reset pin also can also be used to terminate power-down. power-down control several parameters of power-down operation can be controlled through control bits of the power-down/sportl autobuffer con- trol register. this control register is memory-mapped at loca- tion 0x3fef and the power-down control bits are as follows: bit[15] xtal: xtal pin disable during power-down 1 = disabled, 0 = enable (default) bit[14] pwdflag: (read only ) when pwdena = 1, the value of bit [14] pwdflag is equal to the status of the pwdflag input pin. when pwdena = 0, the value of bit [14] pwdflag is equal to 0. bit[13] pwdena: power-down enable 1 = enable, 0 = disable (default) if pwdena is set to 0, then the output pin pwdack is driven low and the input pin pwdflag is disabled note: it is not recommended that power-down enable be set or cleared during an irq2 interrupt. bit[12] pucr: power-up context reset 1 = soft reset, 0 = resume execution (default) entering power-down the power-down sequence is defined as follows: ? enable power-down logic by setting the pwdena bit in the power-down/sportl autobuffer control register. note: in order to power-down, the pwdena bit must be set before the irq2 interrupt is initiated. ? initiate the power-down sequence by generating an irq2 interrupt either externally or by software use of the ifc register. ? the processor vectors to the irq2 interrupt vector located at 0x0004. ? any number of housekeeping instructions, starting at loca- tion 0x0004 can be executed prior to the processor entering the power-down mode. ? the processor enters the power-down mode when the pro- cessor executes an idle instruction while executing the irq2 interrupt routine. notes: ? if an rti instruction is executed before the processor en- counter an idle instruction, then the processor returns from the irq2 interrupt and the power-down sequence is aborted. ? the user can differentiate between a normal irq2 inter- rupt and a power-down irq2 interrupt by resetting the pwdflag pin and checking the status of this pin by testing the pwdflag bit in the power-down/sport1 autobuffer control register located at dm[0x3fef]. rev. 0 adsp-216x C10C exiting power-down the power-down mode can be exited with the use of the pwdflag or reset pin. applying a low-to-high transition to the pwdflag pin takes the processor out of power-down mode. in this case, a delay of 4096 cycles is automatically in- duced by the processor. also, depending on the status of the power-up context reset bit (pucr), the processor either 1) continues to execute instructions following the idle instruc- tion that caused the power-down. a rti instruction is re- quired to pass control back to the main routine (pucr = 0) or 2) resumes operation from power-down by clearing the pc, status, loop and cntr stack. the imask and astat registers are set to 0 and the sstat goes to 0x55. the processor then starts executing instructions from the address zero (pucr = 1). in the case where the power-down mode is exited by asserting the reset pin, the processor state is reset and instruction are executed from address 0x0000. the reset pin in this case must be held low long enough for the external crystal (if any) and the on-chip pll to stabilize and lock. low power idle instruction the idle instruction places the adsp-216x processor in low power state in which it waits for an interrupt. when an interrupt occurs, it is serviced and execution continues with instruction following idle. typically this next instruction will be a jump back to the idle instruction. this implements a low power standby loop. the idle n instruction is a special version of idle that slows the processors internal clock signal to further reduce power consumption. the reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor, n , given in the idle instruction. the syntax of the instruction is: idle n ; where n = 16, 32, 64 or 128. the instruction leaves the chip in an idle state, operating at the slower rate. while it is in this state, the processors other inter- nal clock signals, such as sclk, clkout, and the timer clock, are reduced by the same ratio. upon receipt of an en- abled interrupt, the processor will stay in the idle state for up to a maximum of n clkin cycles, where n is the divisor speci- fied in the instruction, before resuming normal operation. when the idle n instruction is used, it slows the processors internal clock and thus its response time to incoming interruptsC the 1-cycle response time of the standard idle state is increased by n , the clock divisor. when an enabled interrupt is received, the adsp-216x will remain in the idle state for up to a maxi- mum of n clkin cycles (where n = 16, 32, 64 or 128) before resuming normal operation. when the idle n instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processors reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n clkin cycles). adsp-216x prototyping you can prototype your adsp-216x system with either adsp- 2101 or adsp-2103 ram-based processors. when code is fully developed and debugged, it can be submitted to analog devices for conversion into an adsp-216x rom product. the adsp-2101 ez-ice emu lator can be used for development of adsp-216x systems. for the 3.3 v adsp-2162/adsp-2164 and adsp-2166, a voltage converter interface board provides 3.3 v emulation. additional overlay memory is used for emulation of adsp- 2161/adsp-2162 systems. it should be noted that due to the use of off-chip overlay memory to emulate the adsp-2161/ adsp-2162, a performance loss may be experienced when both executing instructions and fetching program memory data from the off-chip overlay memory in the same cycle. this can be overcome by locating program memory data in on-chip memory. ordering procedure for adsp-216x rom processors to place an order for a custom rom-coded adsp-2161, adsp-2162, adsp-2163, adsp-2164 , adsp-2165 or adsp- 2166 processor, you must: 1. complete the following forms contained in the adsp rom ordering package , available from your analog devices sales representative: adsp-216x rom specification form rom release agreement rom nre agreement & minimum quantity order (mqo) acceptance agreement for preproduction rom products 2. return the forms to analog devices along with two copies of the memory image file (.exe file) of your rom code. the files must be supplied on two 3.5" or 5.25" floppy disks for the ibm pc (dos 2.01 or higher). 3. place a purchase order with analog devices for nonrecurring engineering changes (nre) associated with rom product development. after this information is received, it is entered into analog devices rom manager system which assigns a custom rom model number to the product. this model number will be branded on all prototype and production units manufactured to these specifications. to minimize the risk of code being altered during this process, analog devices verifies that the .exe files on both floppy disks are identical, and recalculates the checksums for the .exe file entered into the rom manager system. the checksum data, in the form of a rom memory map, a hard copy of the .exe file, and a rom data verification form are returned to you for inspection. a signed rom verification form and a purchase order for production units are required prior to any product being manu- factured. prototype units may be applied toward the minimum order quantity. upon completion of prototype manufacture, analog devices will ship prototype units and a delivery schedule update for production units. an invoice against your purchase order for the nre charges is issued at this time. there is a charge for each rom mask generated and a mini- mum order quantity. consult your sales representative for de- tails. a separate order must be placed for parts of a specific package type, temperature range, and speed grade. rev. 0 adsp-216x C11C instruction set the adsp-216x assembly language uses an algebraic syntax for ease of coding and readability. the sources and destinations of computations and data movements are written explicitly in each assembly statement, eliminating cryptic assembler mnemonics. every instruction assembles into a single 24-bit word and executes in a single cycle. the instructions encompass a wide variety of instruction types along with a high degree of operational parallelism. t here are five basic categories of instructions: data move instructions, computational instructions, multifunction instructions, program flow control instructions and miscella- neous instructions. multifunction instructions perform one or two data moves and a computation. the instruction set is summarized below. the adsp-2100 family users manual contains a complete reference to the instruction set. alu instructions [if cond] ar|af = xop + yop [+ c] ; add/add with carry = xop C yop [+ cC 1] ; subtract x C y/subtract x C y with borrow = yop C xop [+ cC 1] ; subtract y C x/subtract y C x with borrow = xop and yop ; and = xop or yop ; or = xop xor yop ; xor = pass xop ; pass, clear = C xop ; negate = not xop ; not = abs xop ; absolute value = yop + 1 ; increment = yop C 1 ; decrement = divs yop, xop ; divide = divq xop ; mac instructions [if cond] mr|mf = xop * yop ; multiply = mr + xop * yop ; multiply/accumulate = mr C xop * yop ; multiply/subtract = mr ; transfer mr =0 ; clear if mv sat mr ; conditional mr saturation shifter instructions [if cond] sr = [sr or] ashift xop ; arithmetic shift [if cond] sr = [sr or] lshift xop ; logical shift sr = [sr or] ashift xop by rev. 0 adsp-216x C12C program flow instructions do rev. 0 C13C adsp-216x specifications adsp-2161/adsp-2163/adsp-2165Crecommended operating conditions k grade b grade parameter min max min max unit v dd supply voltage 4.50 5.50 4.50 5.50 v t amb ambient operating temperature 0 +70 C40 +85 c see environmental conditions for information on thermal specifications. electrical characteristics parameter test conditions min max unit v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin and reset voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min, i oh = C0.5 ma 2.4 v @ v dd = min, i oh = C100 m a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min, i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max, v in = v dd max 10 m a i il lo-level input current 3 @ v dd = max, v in = 0 v 10 m a i ozh three-state leakage current 7 @ v dd = max, v in = v dd max 8 10 m a i ozl three-state leakage current 7 @ v dd = max, v in = 0 v 8 10 m a c i input pin capacitance 3, 6, 9 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 6, 7, 9, 10 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 bidirectional pins: d0Cd23, sclk1, rfs1, tfs1, sclk0, rfs0, tfs0. 2 input-only pins: reset , irq2 , br , mmap, dr1, dr0. 3 input-only pins: clkin, reset , irq2 , br , mmap, dr1, dr0. 4 output pins: bg , pms , dms , bms , rd , wr , a0Ca13, clkout, dt1, dt0. 5 although specified for ttl outputs, all adsp-21xx outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-stateable pins: a0Ca13, d0Cd23, pms , dms , bms , rd , wr , dt1, sclk1, rfs1, tfs1, dt0, sclk0, rfs0, tfs0. 8 0 v on br , clkin active (to force three-state condition). 9 applies to plcc, mqfp package types. 10 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . C40 c to +85 c (no extended temperature range) storage temperature range . . . . . . . . . . . . C65oc to +150oc lead temperature (10 sec) pga . . . . . . . . . . . . . . . . . +300oc lead temperature (5 sec) plcc, mqfp, tqfp . . . . +280oc *stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-216x features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. rev. 0 adsp-216x C14C specifications adsp-2161/adsp-2163/adsp-2165Csupply current and power parameter test conditions min max unit i dd supply current (dynamic) 1 @ v dd = max, t ck = 40 ns 2 38 ma @ v dd = max, t ck = 50 ns 2 31 ma @ v dd = max, t ck = 60 ns 2 27 ma i dd supply current (idle) 1, 3 @ v dd = max, t ck = 40 ns 12 ma @ v dd = max, t ck = 50 ns 11 ma @ v dd = max, t ck = 60 ns 10 ma notes 1 current reflects device operating with no output loads. 2 v in = 0.4 v and 2.4 v. 3 idle refers to adsp-21xx state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. for typical supply current (internal power dissipation) figures, see figure 9. specifications subject to change without notice. frequency C mhz 220 180 10.00 200 80 60 idd dynamic 1 v dd = 5.5v v dd = 5.0v v dd = 4.5v 205mw 157mw 118mw 129mw 100mw 74mw power C mw 160 140 120 100 13.83 20.00 25.00 30.00 frequency C mhz 10 30 20 40 0 idd idle 1,2 v dd = 5.5v v dd = 5.0 v dd = 4.5v 35mw 51mw 38mw 28mw power C mw 49mw 64mw 50 60 70 10.00 13.83 20.00 25.00 30.00 valid for all temperature grades. 1 power reflects device operating with no output loads. 2 idle refers to adsp-216x operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 3 maximum power dissipation at v dd = 5.5v during execution of idle n instruction. frequency C mhz 65 40 35 30 idd idle n modes 3 64mw 43mw 42mw 51mw 41mw 40mw power C mw 45 50 55 60 10.00 13.83 20.00 25.00 30.00 idle 16 idle 128 idd idle figure 9. adsp-2161/adsp-2163/adsp-2165 (typical) vs. frequency rev. 0 adsp-216x C15C power dissipation example to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an adsp-2161 application where external data memory is used and no other outputs are active, power dissipation is calcu- lated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 5.0 v and t ck = 50 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation (from figure 9). ( c v dd 2 f ) is calculated for each output: # of output pins 3 c 3 v dd 2 3 f address, dms 8 10 pf 5 2 v 20 mhz = 40.0 mw data, wr 9 10 pf 5 2 v 10 mhz = 22.5 mw rd 1 10 pf 5 2 v 10 mhz = 2.5 mw clkout 1 10 pf 5 2 v 20 mhz = 5.0 mw 70.0 mw total power dissipation for this example = p int + 70.0 mw. environmental conditions ambient temperature rating: t amb = t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package u ja u jc u ca plcc 27 c/w 16 c/w 11 c/w mqfp 60 c/w 18 c/w 42 c/w capacitive loading figures 10 and 11 show capacitive loading characteristics for the adsp-2161/adsp-2163/adsp-2165. c l C pf rise time (0.4v C 2.0v) C ns 0 0 175 25 50 150 1 v dd = 4.5v 8 6 4 100 125 75 7 5 3 2 figure 10. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) c l C pf C3 0 175 25 50 150 v dd = 4.5v 5 3 1 100 125 75 4 2 C2 C1 0 valid output delay or hold C ns figure 11. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) adsp-2161/adsp-2163/adsp-2165 rev. 0 adsp-216x C16C test conditions figure 12 shows voltage reference levels for ac measurements. 1.5v output 3.0v 0.0v input 1.5v 2.0v 0.8v figure 12. voltage reference levels for ac measurements (except output enable/disable) output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured out- put high or low voltage to a high impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in figure 13. the time t measured is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the mea- sured output high or low voltage. the decay time, t decay , is dependent on the capacitative load, c l , and the current load, i l , on the output pin. it can be ap- proximated by the following equation: t cv i decay l l = 05 . from which t dis = t measured C t decay is calculated. if multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. specifications adsp-2161/adsp-2163/adsp-2165 output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in figure 13. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) C 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 13. output enable/disable to output pin 50pf +1.5v i oh i ol figure 14. equivalent device loading for ac measurements (except output enable/disable) rev. 0 adsp-216x C17C adsp-2162/adsp-2164/adsp-2166Crecommended operating conditions k grade b grade parameter min max min max unit v dd supply voltage 3.00 3.60 3.00 3.60 v t amb ambient operating temperature 0 +70 C40 +85 c see environmental conditions for information on thermal specifications. electrical characteristics parameter test conditions min max unit v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin and reset voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.4 v v oh hi-level output voltage 2, 3, 4 @ v dd = min, i oh = C0.5 ma 4 2.4 v v ol lo-level output voltage 2, 3, 4 @ v dd = min, i ol = 2 ma 4 0.4 v i ih hi-level input current 3 @ v dd = max, v in = v dd max 10 m a i il lo-level input current 3 @ v dd = max, v in = 0 v 10 m a i ozh three-state leakage current 5 @ v dd = max, v in = v dd max 6 10 m a i ozl three-state leakage current 5 @ v dd = max, v in = 0 v 6 10 m a c i input pin capacitance 1, 7, 8 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 2, 7, 8, 9 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 input-only pins: clkin, reset , irq2 , br , mmap, dr1, dr0. 2 bidirectional pins: d0Cd23, sclk1, rfs1, tfs1, sclk0, rfs0, tfs0. 3 output pins: bg , pms , dms , bms , rd , wr , a0Ca13, clkout, dt1, dt0. 4 all adsp-2162, adsp-2164 and adsp-2166 outputs are cmos and will drive to v dd and gnd with no dc loads. 5 three-stateable pins: a0Ca13, d0Cd23, pms , dms , bms , rd , wr , dt1, sclk1, rfs1, tfs1, dt0, sclk0, rfs0, tfs0. 6 0 v on br , clkin active (to force three-state condition). 7 guaranteed but not tested. 8 applies to plcc and mqfp package types. 9 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +4.5 v input voltage . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . C40oc to +85oc storage temperature range . . . . . . . . . . . . C65oc to +150oc lead temperature (5 sec) plcc, mqfp . . . . . . . . . . +280oc *stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. rev. 0 adsp-216x C18C specifications adsp-2162/adsp-2164/adsp-2166Csupply current and power parameter test conditions min max unit i dd supply current (dynamic) 1 @ v dd = max, t ck = 60 ns 2 16 ma @ v dd = max, t ck = 76.9 ns 15 ma @ v dd = max, t ck = 97.6 ns 14 ma i dd supply current (idle) 1, 3 @ v dd = max, t ck = 60 ns 5 ma @ v dd = max, t ck = 76.9 ns 4 ma @ v dd = max, t ck = 97.6 ns 4 ma notes 1 current reflects device operating with no output loads. 2 v in = 0.4 v and 2.4 v. 3 idle refers to adsp-216x state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. for typical supply current (internal power dissipation) figures, see figure 15. specifications subject to change without notice. 9mw frequency C mhz 2 6 4 8 0 idd idle 1 8mw 6mw 5mw power C mw 10mw 13mw 10 12 14 5.00 7.00 10.00 15.00 13.83 v dd = 3.6v v dd = 3.30v v dd = 3.0v frequency C mhz 50 40 5.00 45 15 idd dynamic 1,2 v dd = 3.6v v dd = 3.30v v dd = 3.0v 48mw 37mw 29mw 24mw 19mw 15mw power C mw 35 30 25 20 7.00 10.00 13.83 15.00 10 5 0 idd idle n modes 3 13mw 7mw 6mw 9mw 5mw 4mw power C mw idle 16 idle 128 idd idle 2 6 4 8 0 10 12 14 frequency C mhz 5.00 7.00 10.00 15.00 13.83 valid for all temperature grades. 1 power reflects device operating with no output loads. 2 idle refers to adsp-216x operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 3 maximum power dissipation at v dd = 3.6v during execution of idle n instruction. figure 15. adsp-2162 power (typical) vs. frequency) rev. 0 adsp-216x C19C power dissipation example to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an adsp-2162 application where external data memory is used and no other outputs are active, power dissipation is calcu- lated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 3.3 v and t ck = 100 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation (from figure 15). ( c v dd 2 f ) is calculated for each output: # of output pins 3 c 3 v dd 2 3 f address, dms 8 10 pf 3.3 2 v 10 mhz = 8.71 mw data, wr 9 10 pf 3.3 2 v 5 mhz = 4.90 mw rd 1 10 pf 3.3 2 v 5 mhz = 0.55 mw clkout 1 10 pf 3.3 2 v 10 mhz = 1.09 mw 15.25 mw total power dissipation for this example = p int + 15.25 mw. environmental conditions ambient temperature rating: t amb = t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package u ja u jc u ca mqfp 60 c/w 18 c/w 42 c/w adsp-2162/adsp-2164/adsp-2166 capacitive loading figures 16 and 17 show capacitive loading characteristics for the adsp-2162 and adsp-2164. c l C pf rise time (0.4v C 2.0v) C ns 0 0 175 25 50 150 5 v dd = 3.0v 30 20 100 125 75 35 25 15 10 figure 16. typical output rise time vs. load capaci- tance, c l (at maximum ambient operating temperature) c l C pf rise time (0.4v C 2.0v) C ns C4 0 175 25 50 150 v dd = 3.0v 100 125 75 C2 nominal 2 4 6 8 10 figure 17. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) rev. 0 adsp-216x C20C specifications adsp-2162/adsp-2164/adsp-2166 test conditions figure 18 shows voltage reference levels for ac measurements. v dd 2 output input v dd 2 figure 18. voltage reference levels for ac measurements (except output enable/disable) output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the out- put disable time (t dis ) is the difference of t measured and t decay , as shown in figure 19. the time t measured is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the mea- sured output high or low voltage. the decay time, t decay , is dependent on the capacitative load, c l , and the current load, i l , on the output pin. it can be ap- proximated by the following equation: t cv i decay l l = 05 . from which t dis = t measured C t decay is calculated. if multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in figure 19. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) C 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 19. output enable/disable to output pin 50pf i oh i ol v dd 2 figure 20. equivalent device loading for ac measurements (except output enable/disable) rev. 0 adsp-216x C21C timing parameters (adsp-2161/adsp-2163/adsp-2165) general notes use the exact timing information given. do not attempt to de- rive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect sta- tistical variations and worst cases. consequently, you cannot meaningfully add parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. memory requirements the table below shows common memory device specifications and the corresponding adsp-216x timing parameters, for your convenience. adsp-216x memory device specification timing parameter timing parameter definition address setup to write start t asw a0Ca13, dms , pms setup before wr low address setup to write end t aw a0Ca13, dms , pms setup before wr deasserted address hold time t wra a0Ca13, dms , pms hold after wr deasserted data setup time t dw data setup before wr high data hold time t dh data hold after wr high oe to data valid t rdd rd low to data valid address access time t aa a0Ca13, dms , pms , bms to data valid rev. 0 adsp-216x C22C timing parameters (adsp-2161/adsp-2163/adsp-2165) clock signals and reset 16.67 mhz 20 mhz 25 mhz frequency dependency parameter min max min max min max min max unit timing requirements: t ck clkin period 60 150 50 150 40 150 t ck 150 ns t ckl clkin width low 20 20 15 20 ns t ckh clkin width high 20 20 15 20 ns t rsp reset width low 300 250 200 5t ck 1 ns switching characteristics: t cpl clkout width low 20 15 10 0.5t ck C 10 ns t cph clkout width high 20 15 10 0.5t ck C 10 ns t ckoh clkin high to clkout high 0 20 0 20 0 15 2 020 2 ns notes 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles, assuming stable clkin (not including crystal oscillator startup time). 2 for 25 mhz only, the maximum frequency dependency for t ckoh = 15 ns. clkout clkin t cpl t chok t ckl t ckh t ck t cph figure 21. clock signals rev. 0 adsp-216x C23C timing parameters (adsp-2161/adsp-2163/adsp-2165) interrupts and flags 16.67 mhz 20 mhz 25 mhz frequency dependency parameter min max min max min max min max unit timing requirements: t ifs irqx 1 or fi setup before 30 27.5 25 0.25t ck + 15 ns clkout low 2, 3 t ifs irqx 1 or fi setup before 33 30.5 28 0.25t ck + 18 ns clkout low 2, 3 t ifh irqx 1 or fi hold after clkout 15 12.5 10 0.25t ck ns high 2, 3 switching characteristics: t foh fo hold after clkout high 0 0 0 0 ns t fod fo delay from clkout high 15 15 12 4 15 4 ns notes 1 irqx = irq0 , irq1 , and irq2 . 2 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the following cycle. (refer to the interrupt controller section in chapter 3, program control, of the adsp-2100 family users manual , third edition for further information on interrupt servicing.) 3 edge-sensitive interrupts require pulsewidths greater than 10 ns. level-sensitive interrupts must be held low until serviced. 4 for 25 mhz only, the maximum frequency dependency for t fod = 12 ns. t foh clkout flag output(s) irqx fi t ifs t ifh t fod figure 22. interrupts and flags rev. 0 adsp-216x C24C timing parameters (adsp-2161/adsp-2163/adsp-2165) bus request/bus grant 16.67 mhz 20 mhz 25 mhz frequency dependency parameter min max min max min max min max unit timing requirements: t bh br hold after clkout high 1 20 17.5 15 0.25t ck + 5 ns t bs br setup before clkout low 1 35 32.5 30 0.25t ck + 20 ns switching characteristics: t sd clkout high to dms , 35 32.5 30 0.25t ck + 20 ns pms , bms , rd , wr disable t sdb dms , pms , bms , rd , wr 0000 ns disable to bg low t se bg high to dms , pms ,0000 ns bms , rd , wr enable t sec dms , pms , bms , rd , wr 5 2.5 1.5 2 0.25t ck C 10 2 ns enable to clkout high notes 1 if br meets the t bs and t bh setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cyc le. br requires a pulsewidth greater than 10 ns. 2 for 25 mhz only, the minimum frequency dependency formula for t sec = (0.25t ck C 8.5). section 10.2.4, bus request/grant, on page 212 of the adsp-2100 family users manual , third edition, states that when br is recognized, the processor responds immediately by asserting bg during the same cycle. this is incorrect for the current versions of all adsp-21xx processors: bg is asserted in the cycle after br is recognized. no external synchronization circuit is needed when br is generated as an asynchronous signal. clkout t sd t sdb t se t sec t bs br t bh clkout pms , dms bms , rd wr bg figure 23. bus request/bus grant rev. 0 adsp-216x C25C timing parameters (adsp-2161/adsp-2163/adsp-2165) memory read 16.67 mhz 20 mhz 25 mhz parameter min max min max min max unit timing requirements: t rdd rd low to data valid 17 12 7 ns t aa a0Ca13, pms , dms , bms to data valid 27 19.5 12 ns t rdh data hold from rd high 0 0 0 ns switching characteristics: t rp rd pulsewidth 22 17 12 ns t crd clkout high to rd low 10 25 7.5 22.5 5 20 ns t asr a0Ca13, pms , dms , bms setup before rd low 5 2.5 1.5 1 ns t rda a0Ca13, pms , dms , bms hold after rd deasserted 6 3.5 1 ns t rwr rd high to rd or wr low 25 20 15 ns frequency dependency (clkin 25 mhz) parameter min max unit timing requirements: t rdd rd low to data valid 0.5t ck C 13 + w ns t aa a0Ca13, pms , dms , bms to data valid 0.75t ck C 18 + w ns t rdh data hold from rd high 0 switching characteristics: t rp rd pulsewidth 0.5t ck C 8 + w ns t crd clkout high to rd low 0.25t ck C 5 0.25t ck + 10 ns t asr a0Ca13, pms , dms , bms setup before rd low 0.25t ck C 10 1 ns t rda a0Ca13, pms , dms , bms hold after rd deasserted 0.25t ck C 9 ns t rwr rd high to rd or wr low 0.5t ck C 5 ns notes 1 for 25 mhz only, minimum frequency dependency formula for t asr = (0.25t ck C 8.5). w = wait states t ck. clkout a0Ca13 d t rda t rwr t rp t asr t crd t rdd t aa t rdh dms , pms , bms rd wr figure 24. memory read rev. 0 adsp-216x C26C timing parameters (adsp-2161/adsp-2163/adsp-2165) memory write 16.67 mhz 20 mhz 25 mhz parameter min max min max min max unit switching characteristics: t dw data setup before wr high 17 12 7 ns t dh data hold after wr high 5 2.5 0 ns t wp wr pulsewidth 22 17 12 ns t wde wr low to data enabled 0 0 0 ns t asw a0Ca13, dms , pms setup before wr low 5 2.5 1.5 1 ns t ddr data disable before wr or rd low 5 2.5 1.5 1 ns t cwr clkout high to wr low 10 25 7.5 22.5 5 20 ns t aw a0Ca13, dms , pms , setup before wr deasserted 23 15.5 8 ns t wra a0Ca13, dms , pms hold after wr deasserted 6 3.5 1 ns t wwr wr high to rd or wr low 25 20 15 ns frequency dependency (clkin 25 mhz) parameter min max unit switching characteristics: t dw data setup before wr high 0.5t ck C 13 + w ns t dh data hold after wr high 0.25t ck C 10 ns t wp wr pulsewidth 0.5t ck C 8 + w ns t wde wr low to data enabled 0 t asw a0Ca13, dms , pms setup before wr low 0.25t ck C 10 1 ns t ddr data disable before wr or rd low 0.25t ck C 10 1 ns t cwr clkout high to wr low 0.25t ck C 5 0.25t ck + 10 ns t aw a0Ca13, dms , pms , setup before wr deasserted 0.75t ck C 22 + w ns t wra a0Ca13, dms , pms hold after wr deasserted 0.25t ck C 9 ns t wwr wr high to rd or wr low 0.5t ck C 5 ns notes 1 for 25 mhz only, the minimum frequency dependency formula for t asw and t ddr = (0.25t ck C 8.5). w = wait states t ck . clkout a0Ca13 d t wp t aw t cwr t dh t wde t dw t asw t wwr t wra t ddr dms , pms , bms rd wr figure 25. memory write rev. 0 adsp-216x C27C timing parameters (adsp-2161/adsp-2163/adsp-2165) serial ports 13.824 mhz* frequency dependency parameter min max min max unit timing requirements: t sck sclk period 72.3 72.3 ns t scs dr/tfs/rfs setup before sclk low 8 8 ns t sch dr/tfs/rfs hold after sclk low 10 10 ns t scp sclk in width 28 28 ns switching characteristics: t cc clkout high to sclk out 18.1 33.1 0.25t ck 0.25t ck + 15 ns t scde sclk high to dt enable 0 0 ns t scdv sclk high to dt valid 20 20 ns t rh tfs/rfs out hold after sclk high 0 0 ns t rd tfs/rfs out delay from sclk high 20 20 ns t scdh dt hold after sclk high 0 0 ns t tde tfs (alt) to dt enable 0 0 ns t tdv tfs (alt) to dt valid 18 18 ns t scdd sclk high to dt disable 25 25 ns t rdv rfs (multichannel, frame delay zero) 20 20 ns to dt valid *maximum serial port operating frequency is 13.824 mhz for all processor speed grades. clkout sclk tfs dt t cc t cc t scs t sch t rh t scde t scdh t scdd t tde t rdv dr tfs in rfs in rfs out tfs out t tdv t scdv t rd t scp t sck t scp (alternate frame mode) rfs (multichannel mode, frame delay 0 {mfd = 0}) figure 26. serial ports rev. 0 adsp-216x C28C timing parameters (adsp-2162/adsp-2164/adsp-2166) general notes use the exact timing information given. do not attempt to de- rive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect sta- tistical variations and worst cases. consequently, you cannot meaningfully add parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. memory requirements the table below shows common memory device specifications and the corresponding adsp-216x timing parameters, for your convenience. adsp-216x memory device specification timing parameter timing parameter definition address setup to write start t asw a0Ca13, dms , pms setup before wr low address setup to write end t aw a0Ca13, dms , pms setup before wr deasserted address hold time t wra a0Ca13, dms , pms hold after wr deasserted data setup time t dw data setup before wr high data hold time t dh data hold after wr high oe to data valid t rdd rd low to data valid address access time t aa a0Ca13, dms , pms , bms to data valid rev. 0 adsp-216x C29C timing parameters (adsp-2162/adsp-2164/adsp-2166) clock signals and reset frequency 10.24 mhz 13.0 mhz 16.67 mhz dependency parameter min max min max min max min max unit timing requirements: t ck clkin period 97.6 150 76.9 150 60.0 150 t ck 150 ns t ckl clkin width low 20 20 20 20 ns t ckh clkin width high 20 20 20 20 ns t rsp reset width low 488 384.5 300 5t ck 1 ns switching characteristics: t cpl clkout width low 38.8 28.5 20 0.5t ck C 10 ns t cph clkout width high 38.8 28.5 20 0.5t ck C 10 ns t ckoh clkin high to clkout high 0 20 0 20 0 20 0 20 ns note 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable clkin (not including crystal oscillator startup time). clkout clkin t cpl t chok t ckl t ckh t ck t cph figure 27. clock signals rev. 0 adsp-216x C30C timing parameters (adsp-2162/adsp-2164/adsp-2166) interrupts and flags frequency 10.24 mhz 13.0 mhz 16.67 mhz dependency parameter min max min max min max min max unit timing requirements: t ifs irqx 1 or fi setup before clkout low 2, 3 44.4 39.2 35.0 0.25t ck + 20 ns t ifh irqx 1 or fi hold after clkout high 2, 3 24.4 19.2 15.0 0.25t ck ns switching characteristics: t foh fo hold after clkout high 0 0 0 0 ns t fod fo delay from clkout high 15 15 15 15 ns notes 1 irqx = irq0 , irq1 , and irq2 . 2 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the following cycle. (refer to the interrupt controller section in chapter 3, program control, of the adsp-2100 family users manual , third edition, for further information on interrupt servicing.) 3 edge-sensitive interrupts require pulse widths greater than 10 ns. level-sensitive interrupts must be held low until serviced. t foh clkout flag output(s) irqx fi t ifs t ifh t fod figure 28. interrupts and flags rev. 0 adsp-216x C31C timing parameters (adsp-2162/adsp-2164/adsp-2166) bus request/bus grant 10.24 mhz 13.0 mhz 16.67 mhz frequency dependency parameter min max min max min max min max unit timing requirements: t bh br hold after clkout high 1 29.4 24.2 20.0 0.25t ck + 5 ns t bs br setup before clkout low 1 44.4 39.2 35.0 0.25t ck + 20 ns switching characteristics: t sd clkout high to dms , pms , bms , rd , wr disable 44.4 39.2 35.0 0.25t ck + 20 ns t sdb dms , pms , bms , rd , wr disable to bg low 0000 ns t se bg high to dms , pms , bms , rd , wr enable 0 0 0 0 ns t sec dms , pms , bms , rd , wr enable to clkout high 14.4 9.2 5.0 0.25t ck C 10 ns notes 1 if br meets the t bs and t bh setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cyc le. br requires a pulsewidth greater than 10 ns. section 10.2.4, bus request/grant, of the adsp-2100 family users manual , third edition, states that, when br is recognized, the processor responds immedi- ately by asserting bg during the same cycle. this is incorrect for the current versions of all adsp-21xx processors: bg is asserted in the cycle after br is recognized. no external synchronization circuit is needed when br is generated as an asynchronous signal. clkout t sd t sdb t se t sec t bs br t bh clkout pms , dms bms , rd wr bg figure 29. bus request/grant rev. 0 adsp-216x C32C timing parameters (adsp-2162/adsp-2164/adsp-2166) memory read 10.24 mhz 13.0 mhz 16.67 mhz frequency dependency parameter min max min max min max min max unit timing requirements: t rdd rd low to data valid 33.8 23.5 15 0.5t ck C 15 + w ns t aa a0Ca13, pms , dms , bms to data valid 49.2 33.7 21 0.75t ck C 24 + w ns t rdh data hold from rd high 0 0 0 0 ns switching characteristics: t rp rd pulsewidth 43.8 33.25 25 0.5t ck C 5 + w ns t crd clkout high to rd low 19.4 34.4 14.2 29.2 10.0 25.0 0.25t ck C 5 0.25t ck + 10 ns t asr a0Ca13, pms , dms , bms setup before rd low 12.4 7.2 3.0 0.25t ck C 12 ns t rda a0Ca13, pms , dms , bms hold after rd deasserted 14.4 9.2 5.0 0.25t ck C 10 ns t rwr rd high to rd or wr low 38.8 28.5 20.0 0.5t ck C 10 ns w = wait states t ck. clkout a0Ca13 d t rda t rwr t rp t asr t crd t rdd t aa t rdh dms , pms , bms rd wr figure 30. memory read rev. 0 adsp-216x C33C timing parameters (adsp-2162/adsp-2164/adsp-2166) memory write frequency 10.24 mhz 13.0 mhz 16.67 mhz dependency parameter min max min max min max min max unit switching characteristics: t dw data setup before wr high 38.8 28.25 20 0.5t ck C 10 + w ns t dh data hold after wr high 14.4 9.2 5.0 0.25t ck C 10 ns t wp wr pulsewidth 43.8 33.25 25 0.5t ck C 5 + w ns t wde wr low to data enabled 0 0 0 0 t asw a0Ca13, dms , dms setup before wr low 12.4 7.2 3.0 0.25t ck C 12 ns t ddr data disable before wr or rd low 14.4 9.2 5.0 0.25t ck C 10 ns t cwr clkout high to wr low 19.4 34.4 14.2 29.2 10.0 25.0 0.25t ck C 5 0.25t ck + 10 ns t aw a0Ca13, dms , pms , setup before wr deasserted 58.2 42.7 30 0.75t ck C 15 + w ns t wra a0Ca13, dms , pms hold after wr deasserted 14.4 9.2 5.0 0.25t ck C 10 ns t wwr wr high to rd or wr low 38.8 28.25 20 0.5t ck C 10 ns w = wait states t ck. clkout a0Ca13 d t wp t aw t cwr t dh t wde t dw t asw t wwr t wra t ddr dms , pms , bms rd wr figure 31. memory write rev. 0 adsp-216x C34C timing parameters (adsp-2162/adsp-2164/adsp-2166) serial ports 10.24 mhz 13.0 mhz 13.824 mhz 1 frequency dependency parameter min max min max min max min max unit timing requirements: t sck sclk period 97.6 76.9 72.3 1 t ck 1 ns t scs dr/tfs/rfs setup before sclk low 8 8 8 8 ns t sch dr/tfs/rfs hold after sclk low 10 10 10 10 ns t scp sclk in width 28 28 28 28 ns switching characteristics: t cc clkout high to sclk out 24.4 39.4 19.2 34.2 18.1 33.1 0.25t ck 0.25t ck + 15 ns t scde sclk high to dt enable 0 0 0 0 ns t scdv sclk high to dt valid 28 2 20 20 20 2 ns t rh tfs/rfs out hold after sclk high 0 0 0 0 ns t rd tfs/rfs out delay from sclk high 28 2 20 20 20 2 ns t scdh dt hold after sclk high 0 0 0 0 ns t tde tfs (alt) to dt enable 0 0 0 0 ns t tdv tfs (alt) to dt valid 18 18 18 18 ns t scdd sclk high to dt disable 30 2 25 25 25 2 ns t rdv rfs (multichannel, frame 20 delay zero) to dt valid 20 20 20 20 ns notes 1 maximum serial port operating frequency is 13.824 mhz for all processor speed grades faster then 13.824 mhz. 2 for 10.24 mhz only, the maximum frequency dependency for t scdv = 28 ns, t rd = 28 ns, t scdd = 30 ns. clkout sclk tfs dt t cc t cc t scs t sch t rh t scde t scdh t scdd t tde t rdv dr tfs in rfs in rfs out tfs out t tdv t scdv t rd t scp t sck t scp (alternate frame mode) rfs (multichannel mode, frame delay 0 {mfd = 0}) figure 32. serial ports rev. 0 adsp-216x C35C plcc pin number name 52 fo (dt1) 53 irq1 (tfs1) 54 irq0 (rfs1) 55 fi (dr1) 56 sclk1 57 v dd 58 d0 59 d1 60 d2 61 d3 62 d4 63 d5 64 d6 65 d7 66 d8 67 d9 68 d10 plcc pin number name 1 d11 2 gnd 3 d12 4 d13 5 d14 6 d15 7 d16 8 d17 9 d18 10 gnd 11 d19 12 d20 13 d21 14 d22 15 d23 16 v dd 17 mmap plcc pin number name 18 br 19 irq2 20 reset 21 a0 22 a1 23 a2 24 a3 25 a4 26 v dd 27 a5 28 a6 29 gnd 30 a7 31 a8 32 a9 33 a10 34 a11 plcc pin number name 35 a12 36 a13 37 pms 38 dms 39 bms 40 bg 41 xtal 42 clkin 43 clkout 44 wr 45 rd 46 dt0 47 tfs0 48 rfs0 49 gnd 50 dr0 51 sclk0 pin configurations 68-lead plcc 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 21 27 43 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 961 8 7 6 5 68 67 66 65 64 63 62 4321 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pin 1 identifier top view (not to scale) d2 d1 d0 a9 a6 a7 a8 a10 a11 d9 d6 d8 d7 d3 d10 d4 d5 d18 d15 d14 d13 d12 d17 d16 d11 gnd xtal clkin clkout v dd sclk1 fi irq0 gnd d19 d20 d21 d22 d23 v dd mmap br irq2 reset irq1 fo sclk0 dr0 adsp-216x a0 a1 a2 a3 a4 v dd gnd rfs0 tfs0 dt0 rd wr a5 gnd a12 a13 bms bg dms pms rev. 0 adsp-216x C36C pin configurations 80-lead mqfp 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 56 57 58 59 54 55 52 53 50 51 60 45 46 47 48 43 44 42 49 41 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 12 pin 1 identifier top view (not to scale) 40 39 38 37 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 36 v dd a4 a3 a2 a1 a0 reset irq2 br mmap v dd d23 d22 d21 d20 d19 gnd gnd clkout wr rd dt0 tfs0 rfs0 gnd gnd dr0 sclk0 fo irq0 fi sclk1 v dd d0 d1 d2 d18 d17 d16 d15 d14 d13 d12 gnd gnd d11 d10 d9 d8 d6 d5 d4 nc nc nc a5 a6 gnd gnd a7 a8 a9 a10 a11 a12 a13 pms dms bg bms xtal clkin *pwdack nc d3 adsp-216x v dd irq1 *pwdflag d7 v dd nc = no connect mqfp pin number name 1a5 2a6 3gnd 4gnd 5a7 6a8 7a9 8 a10 9 a11 10 a12 11 a13 12 pms 13 dms 14 bms 15 bg 16 xtal 17 clkin 18 pwdack* 19 pwdflag* 20 nc mqfp pin number name 21 clkout 22 wr 23 rd 24 dt0 25 tfs0 26 rfs0 27 gnd 28 gnd 29 dr0 30 sclk0 31 fo (dt1) 32 irq1 (tfs1) 33 irq0 (rfs1) 34 fi (dr1) 35 sclk1 36 v dd 37 d0 38 d1 39 d2 40 d3 mqfp pin number name 41 nc 42 nc 43 nc 44 d4 45 d5 46 d6 47 d7 48 d8 49 d9 50 d10 51 d11 52 gnd 53 gnd 54 d12 55 d13 56 d14 57 d15 58 d16 59 d17 60 d18 mqfp pin number name 61 gnd 62 gnd 63 d19 64 d20 65 d21 66 d22 67 d23 68 v dd 69 v dd 70 mmap 71 br 72 irq2 73 reset 74 a0 75 a1 76 a2 77 a3 78 a4 79 v dd 80 v dd *adsp-2165/adsp-2166 only. others nc. rev. 0 adsp-216x C37C outline dimensions adsp-216x 68-lead plastic leaded chip carrier (plcc) 9 pin 1 identifier 10 61 60 26 27 44 43 top view (pins down) 0.995 (25.27) 0.985 (25.02) sq 0.954 (24.23) 0.950 (24.13) sq 0.019 (0.48) 0.017 (0.43) 0.050 (1.27) typ 0.925 (23.50) 0.895 (22.73) 0.029 (0.74) 0.027 (0.69) 0.104 (2.64) typ 0.175 (4.45) 0.169 (4.29) bottom view (pins up) pin 1 identifier rev. 0 adsp-216x C38C outline dimensions adsp-216x 80-lead plastic quad flatpack (mqfp) seating plane 0.134 (3.40) max 0.041 (1.03) 0.031 (0.78) 0.004 (0.10) max 0.120 (3.05) 0.100 (2.55) 0.010 (0.25) min 0.014 (0.35) 0.010 (0.25) 0.690 (17.45) 0.667 (16.95) 0.555 (14.10) 0.547 (13.90) 0.555 (14.10) 0.547 (13.90) 0.690 (17.45 0.667 (16.95) 1 20 21 41 40 60 61 80 0.486 (12.35) bsc 0.486 (12.35) bsc top view (pins down) 0.026 (0.65) bsc the actual position of each lead is within 0.0047 (0.12) from its ideal position when measured in the lateral direction. rev. 0 adsp-216x C39C ordering guide ambient temperature instruction package package part number 1 range rate (mhz) description option adsp-2161kp-66 2 0 c to +70 c 16.67 68-lead plcc p-68a adsp-2161bp-66 2 C40 c to +85 c 16.67 68-lead plcc p-68a adsp-2161ks-66 2 0 c to +70 c 16.67 80-lead mqfp s-80 adsp-2161bs-66 2 C40 c to +85 c 16.67 80-lead mqfp s-80 adsp-2162kp-40 (3.3 v) 2 0 c to +70 c 10.24 68-lead plcc p-68a adsp-2162bp-40 (3.3 v) 2 C40 c to +85 c 10.24 68-lead plcc p-68a adsp-2162ks-40 (3.3 v) 2 0 c to +70 c 10.24 80-lead mqfp s-80 adsp-2163kp-66 2 0 c to +70 c 16.67 68-lead plcc p-68a adsp-2163bp-66 2 C40 c to +85 c 16.67 68-lead plcc p-68a adsp-2163ks-66 2 0 c to +70 c 16.67 80-lead mqfp s-80 adsp-2163bs-66 2 C40 c to +85 c 16.67 80-lead mqfp s-80 ADSP-2163KP-100 2 0 c to +70 c 25 68-lead plcc p-68a adsp-2163bp-100 2 C40 c to +85 c 25 68-lead plcc p-68a adsp-2163ks-100 2 0 c to +70 c 25 80-lead mqfp s-80 adsp-2163bs-100 2 C40 c to +85 c 25 80-lead mqfp s-80 adsp-2164kp-40 (3.3 v) 2 0 c to +70 c 10.24 68-lead plcc p-68a adsp-2164bp-40 (3.3 v) 2 C40 c to +85 c 10.24 68-lead plcc p-68a adsp-2164ks-40 (3.3 v) 2 0 c to +70 c 10.24 80-lead mqfp s-80 adsp-2164bs-40 (3.3 v) 2 C40 c to +85 c 10.24 80-lead mqfp s-80 adsp-2165ks-80 0 c to +70 c 20.00 80-lead mqfp s-80 adsp-2165ks-100 0 c to +70 c 25.00 80-lead mqfp s-80 adsp-2165bs-80 C40 c to +85 c 20.00 80-lead mqfp s-80 adsp-2165bs-100 C40 c to +85 c 25.00 80-lead mqfp s-80 adsp-2166ks-52 (3.3 v) 0 c to +70 c 13.00 80-lead mqfp s-80 adsp-2166ks-66 (3.3 v) 0 c to +70 c 16.67 80-lead mqfp s-80 adsp-2166bs-52 (3.3 v) C40 c to +85 c 13.00 80-lead mqfp s-80 adsp-2166bs-66 (3.3 v) C40 c to +85 c 16.67 80-lead mqfp s-80 notes 1 k = commercial temperature range (0 c to +70 c). b = industrial temperature range (C40 c to +85 c). p = plcc (plastic leaded chip carrier). s = mqfp (plastic quad flatpack). 2 minimum order quantities required. contact factory for further information. 3 refer to the section titled ordering procedure for rom-coded adsp-216x processors for information about rom coded parts. c3511C3C10/99 printed in u.s.a. |
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